1. Field of the Invention
The present invention relates generally to the design and testing of integrated circuits. More specifically, but without limitation thereto, the present invention relates to the design and testing of logic for detecting transition delay faults in an integrated circuit.
2. Description of Related Art
Early methods for testing integrated circuits were designed to detect stuck-at faults, which may be detected using only a single value at each register of an integrated circuit design. As integrated circuits became larger and more difficult to test, delay fault testing was introduced to detect slow to rise or slow to fall time at a gate input. Detection of delay faults, also called transition delay faults, require two test patterns to be applied to each register.
Integrated circuits (ICs) are susceptible to manufacturing defects that may cause the IC to malfunction, called faults. Two important categories of fault models are single stuck-at faults (SAF) and transition delay faults (TDF). Stuck-at faults occur when a signal inside the ASIC that was designed to transition between two logic states (0 and 1) remains in one state due to a chip manufacturing defect. A transition delay fault occurs when a signal transitions too late or too slow for proper operation due to, for example, excessive net capacitance. Stuck-at faults may be detected using only a single value at each register of an integrated circuit design, while transition delay faults require two test patterns to be applied to each register.
To determine whether an IC has a fault, the IC is typically tested using automated test equipment (ATE) to detect and reject defective parts before shipment to a customer. The number of faults that may be detected by ATE using a test devised by the manufacturer is typically expressed as a percentage of the total number of possible faults and is called the fault coverage of the test. A high value of fault coverage is desirable to avoid the costs associated with delivering defective parts.